Power Optimization in CMOS based EX-OR Gate using Pass Transistor Technique

In the near future, electronic devices will become even smaller to ensure the necessary portability. Therefore, people expect devices to become lighter. The size and weight of the device directly affect the power consumption of electronic devices. Due to these factors, the cost of the device is not completely determined. Therefore, in order to reduce the cost of the device and improve its mobility function, the reduction in size must be achieved by reducing the power consumption of the device and reducing the circuit area. These goals can be achieved by applying faster timing circuits, which allows faster devices to be obtained. To accelerate semiconductors, the limit voltage must also be lowered. However, the current distribution due to the lower limit voltage is a disadvantage. As the hardware becomes smaller, power losses occur in active and standby modes, because power losses below the edge cause a significant loss of control. In any case, various efforts have been made to achieve low power consumption in CMOS VLSI circuits. We have designed EX-XOR gate in this paper with the help of PT and ST. PT technique is design with and without buffer and implement EX-XOR gate. With the help of DSCH, have drawn our EX-XOR CMOS circuit and power dissipation (PD) calculate by MICROWIND software.