Digital CMOS VLSI Implementation and Assessment of Power Efficient Delay Flip-Flop Using Dynamic CMOS Logic for Low Power VLSI Systems

Generally, the flip-flops are vital circuit and foremost power in considering various digital VLSI circuits. In this work, a unique power effective flip-flop, named 5- Device count duple edge triggering delay flipflop (5DCDETFF) is introduced by using the power effective techniques such as reduction of entire quantity of devices usage, implicit triggering clock, duple edge triggering, dynamic CMOS and pass transistor logic schema. By following the dynamic and pass transistor logic design styles, the branch-1 and branch-2 of Flip-flop is realized respectively, with entirely 5 devices count. Another most power proficient techniques called duple edge triggering is used in this projected flip-flop and samples the data input D at an arrival of both up and down edges of the Triggering clock. Instead separate external trigger clock generation network, the triggering clock is directly applied to the branch-1 input terminal as implicit fashion. It lessens the extra transistors usage for clock generation network and also diminishes the power wastage. The presented flip flop is simulated using CMOS 6-metal 0.12μm technology and assessed in point of Complete device usage count, count of Count of clock triggered device, Circuit layout area, Input Data D – Q output delay, global power intake and also in view of product of power delay, Energy delay and power energy products. The anticipated topology intakes the entire power of 5.181μW and accomplishes the power efficacy from 12.85% to 37.92%, which states this foreseen flipflop will be pertinent for low power digital VLSI organisations.