Optimized Level Shifter with Logic Error Correction

In a mobile phone/computer, a total package of electronic components/electronic systems is integrated. Each of the components requires a different voltage range for its work. Providing multiple voltages leads to high power consumption. In such cases, electronic components called Level Shifters (LS) are necessary for voltage shifting or converting to the required levels. Instead of the multi-voltage scheme, single voltage supply and converting it to different voltages provide robust performance, reduced power consumption, and reduces the delay in providing the level-shifted output of any supply voltage. This paper proposes an optimized level shifter with logic error correction circuit (LS-LECC). The logic error correction circuit helps to pull down the output of LS with least delay at the falling transition of the input. The working range of this level shifter circuit is between 0.4-1.2 V at the frequency range of 1 Hz to 1 GHz. All the proposed level shifters and a few existing circuits are designed using Cadence Virtuoso, 45 nm technology and compared their various parameters. LS with a correction circuit can shift the voltage of 0.185 V to 1.2 V for the pulse inputs of low frequencies to 0.001 MHz with a delay of 0.15 ns, that is 32% less than the delay of existing literature. To reduce the delay furthermore, the body bias technique is implemented with the LS-LECC. With this second proposed circuit, delay is reduced by 63.63% with a slight compromise in the static power consumption. The number of transistors in both proposed designs ais reduced by 29%. So, to use the circuit in delay-sensitive cases, proposed LS-LECC with body bias is used and to use the circuit in power-sensitive cases, proposed LS-LECC without body bias can be used.