Meta-learning and U-Net Hybrid-based Defect Identification Method for Converter Valve Thyristor Gate Pole Line Shedding Defects

To accurately recognize images of thyristor gate pole line shedding, a substantial amount of training samples is required. However, in practical engineering applications, such samples are severely lacking. For this reason, this paper proposes a defect recognition method based on a hybrid of meta-learning and U-net for converter valve thyristor gate pole line shedding, which enhances the model training under the condition of small samples, avoids overfitting, and improves the model accuracy. The method makes full use of the meta-training method, which is suitable for the small sample training process, to construct an improved U-net network, which fully safeguards the detailed information of the model feature map through the down-sampling and up-sampling process, and the image edge recognition is more accurate. Comparative analysis of recognition methods using meta-learning and without meta-learning respectively shows that the proposed method improves the recognition rate of thyristor gate line shedding defects in a small sample set size, and the accuracy of this method can reach 100<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">%</sup> for 60 defect images recognition, which is of great significance in engineering applications.