Mitigating Ground Bounce Noise With Super Stacking Structure For Energy Efficient Mpsoc

Objective: Power gating approach placed a vital role in complex architectures to attain high energy efficiency and reduce the leakage power in most of the embedded applications, Multi-Processor System on Chip (MPSoC), etc. But power gating method generates ground bouncing noise during the mode of operation changes.Methods: To mitigate this limitation, Super Stacking Power Gating (SSPG) technique is proposed which exploits the stacking effect to achieve high energy efficiency with less ground bouncing noise. SSPG based CMOS inverter is designed and simulated in Tanner EDA with 125nm technology.Findings: The evaluation results shows that, the proposed SSPG reduces the leakage power by 25.38%, 32.71%, 40.24%, 30.65%, 15.45%, 26.65%, 31.82%, 12.37% and 24.86%. Novelty: When compared with Sleep transistor, Dual Sleep, Dual Stack, Sleepy Stack, Leakage Control Transistor (LECTOR), Sleepy Keeper, VLSI CMOS Leakage Reduction Technique (VCLEARIT), Gated Leakage Transistor (GALEOR) approach and Sleepy Pass gate approach. It also cut down the ground bouncing noise for two possible inputs of CMOS inverter as ‘0’ by 62.16%, 59.42%, 55.55%, 58.20%, 54.83%, 52.54%, 41.66%, 36.36%, 20% and input as ‘1’ by 58.53%, 53.42%, 50.72%, 53.42%, 50.72%, 47.69%, 40.35%, 32%, 12.82% over other ground bouncing noise mitigation approaches.