A Compact Writing Scheme for the Reliability Challenges in 1T Multi-Level FeFET Array: Variation, Endurance, and Write Disturb

Multi-level cell (MLC) ferroelectric FETs (FeFETs) face critical reliability challenges including variation, endurance and write disturb. In this work, we proposed an innovative solution to tackle all the three challenges within a compact writing scheme. Combining error correction, endurance recovery, and self-compensated writing, the proposed scheme achieves a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gt 6\times $ </tex-math></inline-formula> reduction in error ratio (ER), a >100 improvement in endurance, and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\gt 7\times $ </tex-math></inline-formula> reduction in Vth shift. Reliable 2 bits/cell storage with high endurance of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{8}}$ </tex-math></inline-formula> cycles and write-disturb immunity is experimentally demonstrated in the fabricated 1T FeFET array. This writing scheme is realized within a single work flow, and can be readily implemented in the operation circuits.