The Advanced Failure Analysis Methods Based on Dynamic Hot Electron Analyzer and IDD3P Measurements for HKMG Sub-nm DRAM

Abstract In this paper, we propose an advanced failure analysis method for specifying the location of gate-related fails in the High-k Metal Gate (HKMG) MOSFET. The test sample for this experiment is the sub-15nm technology DRAM (Dynamic Random Access Memory) which consists of high speed HKMG transistors. In terms of HKMG transistors, the modification of gate materials and process schemes provoke the various gate related failures in DRAM which makes it more difficult to examine the sample with conventional analyzing methods. So, IDD3P measurement methods along with dynamic Hot Electron Analyzer (HEA) were employed as an advanced fault localization method. IDD3P measurement data provides word-line (WL) dependent failure types which distinguishes the gate-related failures from other irrelevant failures. From the dynamic HEA with the MAGNUM tester, the accurate failure sites can be obtained. Newly combined two analytical methods that we present in this paper are effective in localizing the failure sites more accurate than previously suggested methods.