Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies

Abstract As System-on-a-Chip (SoC) continues to increase in complexity, multiple functionalities are being integrated into one integrated circuit (IC). This requires optimization of Design-for-Testability (DFT) strategies to minimize test time while still ensuring full test coverage of the entire chip. It has led to the widespread adoption of Tessent Streaming Scan Network (SSN) architecture on advanced technology nodes. Unlike traditional scan architectures that send data directly to the scan chains, SSN breaks down the data into packets and optimizes the delivery of these packets to allow efficient, concurrent testing of any number of cores. However, SSN presents a challenge for failure analysis, as it becomes extremely difficult to directly modify the SSN patterns on the fly to create a stimulus that will be used for many of the electrical fault isolation (EFI) techniques such as Laser Voltage Imaging (LVI) and Probing (LVP), Dynamic Laser Stimulation (DLS) and Photon Emissions Analysis (PEM). Key challenges include the inability to loop test patterns, run periodic sequences and no visibility of the scan control and clock signals, since these signals are internally generated by the SSH during retargeting. This paper introduces a new Tessent DFT enhancement developed by Siemens called the “LVX mode”. It is the first feature designed to enable Failure Analysis within a DFT tool, utilizing specific DFT hardware for implementation. In addition, another DFT feature which enables writing special pattern annotations that will indicate the start and end of a capture window and the location of all the capture pulses within that window for a particular pattern will also be presented, together with a methodology that will enable static Photon Emissions on SSN patterns. Since on-the-fly modification of the patterns is not possible in SSN, this paper will present two methods that would allow for a more effective and efficient DLS looping. Lastly, the paper will showcase multiple use cases that demonstrate the effectiveness of these identified DFT enhancements for FA.

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Publication Details

Journal
Proceedings - International Symposium for Testing and Failure Analysis
Published
2024-10-23
DOI
https://doi.org/10.31399/asm.cp.istfa2024p0125
Citations
1
Primary Topic
Electrical Fault Detection and Protection
Type
article
Field-Weighted Citation Impact
0.21
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Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies

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Proceedings - International Symposium for Testing and Failure Analysis
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article

Solving Complex Electrical Fault Isolation Challenges with Innovative DFT Strategies

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article en
1 citations

Abstract

Abstract As System-on-a-Chip (SoC) continues to increase in complexity, multiple functionalities are being integrated into one integrated circuit (IC). This requires optimization of Design-for-Testability (DFT) strategies to minimize test time while still ensuring full test coverage of the entire chip. It has led to the widespread adoption of Tessent Streaming Scan Network (SSN) architecture on advanced technology nodes. Unlike traditional scan architectures that send data directly to the scan chains, SSN breaks down the data into packets and optimizes the delivery of these packets to allow efficient, concurrent testing of any number of cores. However, SSN presents a challenge for failure analysis, as it becomes extremely difficult to directly modify the SSN patterns on the fly to create a stimulus that will be used for many of the electrical fault isolation (EFI) techniques such as Laser Voltage Imaging (LVI) and Probing (LVP), Dynamic Laser Stimulation (DLS) and Photon Emissions Analysis (PEM). Key challenges include the inability to loop test patterns, run periodic sequences and no visibility of the scan control and clock signals, since these signals are internally generated by the SSH during retargeting. This paper introduces a new Tessent DFT enhancement developed by Siemens called the “LVX mode”. It is the first feature designed to enable Failure Analysis within a DFT tool, utilizing specific DFT hardware for implementation. In addition, another DFT feature which enables writing special pattern annotations that will indicate the start and end of a capture window and the location of all the capture pulses within that window for a particular pattern will also be presented, together with a methodology that will enable static Photon Emissions on SSN patterns. Since on-the-fly modification of the patterns is not possible in SSN, this paper will present two methods that would allow for a more effective and efficient DLS looping. Lastly, the paper will showcase multiple use cases that demonstrate the effectiveness of these identified DFT enhancements for FA.

Proceedings - International Symposium for Testing and Failure AnalysisVol. 84918
Google (United States) (US), Digital Science (United States) (US)
Openalex Percentile: Top 47%
Electrical Fault Detection and Protection
0.21
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