Combining Electrical Fault Isolation and Electrical Characterization Inside an SEM to Locate and Characterize Gate Leakages on a 3 nm Device

Abstract This work employs an easy-to-use method to quickly find and characterize leakage currents on a semiconductor sample by combining electrical fault isolation and electrical measurements. By using a simple add-on for a probing system’s tip holders, a prober is transformed into a scanning device that measures currents through a sample’s surface and visualizes the currents in a 2D color map that can be superimposed onto the SE image. As a case study, an area of 1.5 µm x 1.5 µm of a 3 nm device was scanned while the current through the contacts was measured and visualized with Current Imaging (CI) and gate currents were characterized. One leaking gate could be identified and the position of the failure was localized using Electron Beam Induced Resistance CHange (EBIRCH) imaging. This technique also avoids any damage caused by electron beam irradiation as the beam can be switched off during scanning.