Addressing the Cost and Execution Challenges of Scan Chain Testing and Failure Analysis of Complex IC’s

Abstract Analyzing scan chain failures is challenging without dedicated test hardware. Traditional solutions like ATE testers and compact diagnosis tools have significant drawbacks: they're expensive, require complex hardware customization and proprietary software licenses, and need substantial lab space. This paper presents a cost-effective alternative: a portable, flexible, and fully customizable bench-top scan chain testing system that easily integrates with fault isolation tools. Using an off-the-shelf embedded development tool, we replicated the complete scan chain testing process—from pattern generation to test vector transmission/reception and results comparison. The system reduces costs by approximately 200-fold compared to traditional solutions. We validated our approach by analyzing a device with marginal and frequency-dependent stuck-at-scan failures. Using DALS (Dynamic Analog Laser Stimulation), we successfully localized the defect and confirmed it through mechanical delayering, FIB cross-sectioning, and SEM imaging.