Analysis of 3row Failure Caused by Vulnerable Data Retention Failure Adjacent to Disconnected BCAT

Abstract As dynamic random access memory (DRAM) chips grow in density and complexity, tightly packed word lines become increasingly susceptible to interference, potentially causing data retention failures. This study investigates a novel failure mechanism where disconnected buried channel array transistors (BCATs) create interference affecting three adjacent word lines (3row failure). Through systematic analysis of voltage, temperature, and operational sequences, we demonstrate that the pass gate effect significantly impairs dynamic data retention, leading to these 3row failures. Our findings reveal a previously unidentified defect mechanism in advanced DRAM technology and emphasize the importance of comprehensive testing protocols for detecting and characterizing emerging failure modes. This work contributes to the broader effort of improving DRAM reliability in modern computing systems.