Narrowing the Launch and Capture Pulses for Detection of Marginal Defects

Abstract Customer-reported device failures that cannot be replicated during incoming retests present a significant challenge in semiconductor testing. These discrepancies often arise because customer applications subject devices to more extensive and prolonged stress conditions than standard final testing procedures allow. This paper presents a novel method for detecting subtle marginalities in main logic failures by modifying launch and capture pulses in transition delay patterns. Our approach enhances failure detection capabilities in failure analysis environments, particularly for marginal failures that initially pass automated test equipment (ATE) retesting despite customer-reported issues. We demonstrate the effectiveness of this technique through a case study where we successfully reproduced a customer-observed failure by adjusting the timing parameters. This method bridges the gap between standard test conditions and real-world application environments, enabling more accurate fault detection and validation.