A Comprehensive Approach for Post Silicon Unique Hold Time Violation Debug on Ethernet Interface Issue

Abstract Unique frequency dependent hold time violation debug seen on Ethernet IP that caused at least 50% yield loss is showcased in this paper. This debug exposed the process variation issue seen, limitation in current FPGA timing sign-off methodology and design limitation that led to this rare hold time behavior. Customized ATPG patterns has become de facto for effective HVM screening including exploration of new path hold time fault pattern generation. The debug was backed by tester level and system validation debug with help from optical probing and FIB to confirm the root cause and silicon fixes required.