A Quantitative and Automated Quality Metric for Delayering Integrated Circuits
Abstract Integrated circuit (IC) delayering is highly subjective, as operators must make process decisions based on minute details observed in optical images of the ICs. Process decisions have a strong influence on the quality of the final sample, with the result being highly dependent on an operator’s technique, skill, and experience. However, end point detection, process development, and in-process feedback all benefit from a quantitative method to evaluate results. To this end, a quality metric for IC delayering based solely on optical images has been developed. The optical images are processed into CIE-Lab color space, candidate zones are established, and color homogeneity both within and among these zones is calculated, which contribute to a final die quality score. The work done in this study takes a significant step forward in quantifying IC delayering results, which is critical for improving repeatability, reproducibility, and developing automation frameworks in these workflows.
Authors
- Jon Scholl
- J. Timothy Balint (ORCID: https://orcid.org/0000-0002-5940-8495)
- Yash Patel (ORCID: https://orcid.org/0000-0003-3186-5253)
- Adam Kimura (ORCID: https://orcid.org/0000-0002-5141-2182)
- Noah Padro
- Matt Sale
- Nick Harner
Institutions
- United States Air Force Research Laboratory (US)
- Battelle (US)
Publication Details
- Journal
- Proceedings - International Symposium for Testing and Failure Analysis
- Published
- 2024-10-23
- DOI
- https://doi.org/10.31399/asm.cp.istfa2024p0363
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00