Scanning Capacitance Microscopy Application for Top-down Sample Failure Analysis on SOI and Bulk Silicon Wafers

Abstract Scanning Capacitance Microscopy (SCM) is an essential technique in semiconductor failure analysis. It is widely known in studies of dopant profiles and carrier concentration. Not only that, SCM can be utilized as an electrical fault isolation tool to localize a failing transistor. Compared to Conductive Atomic Force Microscopy CAFM, the main advantage of SCM is that it can be used on both Silicon on Insulator (SOI) and Bulk Silicon wafers. In addition, SCM can scan over a relatively large area in a shorter time than conventional nanoprobing methods. This paper presents case studies illustrating the effectiveness of SCM for die level top-down failure analysis on 45nm node SOI and 14nm FinFET bulk Si technologies.