Innovative Fault Localization Techniques for ATPG Failures in Wire-Bonded BGA Packages

Abstract Digital fault localization for semiconductor devices failing Automatic Test Pattern Generation (ATPG) tests can be a very challenging task, particularly when the package of the device does not lend itself towards dynamic stimulation techniques. In the case of wire-bonded Ball-Grid-Array (BGA) devices, complete electrical functionality may only be preserved when access to the die is done from the frontside of the unit. This imposes significant limitations to the applicable optical fault isolation (OFI) techniques and their resolution in highlighting an anomaly, especially in advanced technology nodes that incorporate several metal layers. This paper explores the use of digital VDDLV supply domains as a means of activating defects inside specific logic areas, as an alternative to complex electrical setups, thus overcoming the package related limitations.