A Compact 21-25 GHz Charge-Domain Fractional-N ADPLL with 168 fs Total RMS Jitter

We propose a fractional-N ADPLL featuring a phase detector (PD) operating in charge-domain by charge-steering sampling of a sinusoidal reference waveform. The periodic fractional-N phase error pattern is compensated by an implicit C-DAC taking on the conventional role of a digital-to-time converter. By re-interpreting the multi-bit PD output as mid-rise encoded, its gain is boosted by bang-bang effects, thus mitigating the slow slope of reference waveform, while avoiding the disadvantages of prior-art bang-bang PDs. Total rms jitter is $96 \mathrm{fs}-\mathrm{rms}$ at 24 GHz with reference spurs of −60 dBc in integer-N, while 168 fs with worst in-band spurs of −46 dBc in a fractional-N mode. The occupied area is only $0.08 \mathrm{~mm}^{2}$.