P-type Extended Drain MOSFET integration on thin SOI

In this paper, we demonstrate for the first time the functionality of a P-type eDMOS on thin Silicon-OnInsulator (SOI, 23nm $\mathrm{Si}-25 \mathrm{~nm}$ BOX), with breakdown voltage $B V=17 \mathrm{~V}, R_{O N} X S=5.9 \mathrm{~m} \Omega. \mathrm{mm}^{2}$, and $\mathrm{I}_{\mathrm{OFF}}=2 \mathrm{pA} / \mu \mathrm{m}$ at $\mathrm{V}_{\mathrm{DS}}=-7 \mathrm{~V}$. The 23 nm Si film is sufficiently thick to enable high BV while also being thin enough to allow flexibility through the back-gate and to restrict Floating Body effects. In order to address specific application requirements, the breakdown voltage and ONresistance ($B V, R_{O N}$) tradeoffs can be optimized with the extension doping and length, as well as the back-gate bias. These results demonstrate the feasibility of SOI P-eDMOS cointegration with thin SOI CMOS technologies for highvoltage and high-power applications such as DC-DC converters for power management.