A 0.0045 mm<sup>2</sup> 31.5uW 312.5kHz-BW 2nd-Order Noise-shaping SAR ADC with a Dynamic-BulkSwitching Single-Transistor Amplifier
This paper presents an area-compact noise-shaping (NS) SAR ADC with a $2^{\text {nd }}$-order error-feedback (EF) loop filter, which features a power-efficient single-transistor amplifier (STA) with a dynamic-bulk-switching scheme. The prototype chip achieves 76 dB SNDR over a 312.5 kHz bandwidth with a power consumption of 31.5 uW from a 0.9 V supply, resulting in a Schreier FoM of 176dB and occupying an area of $0.0045 \mathrm{~mm}^{2}$.
Authors
- Le Ye (ORCID: https://orcid.org/0000-0003-0599-7762)
- Siyuan Ye (ORCID: https://orcid.org/0000-0003-0595-4682)
- Jiajia Cui (ORCID: https://orcid.org/0009-0007-4110-2467)
- Xinhang Xu (ORCID: https://orcid.org/0009-0002-1889-7955)
- Zhuoyi Chen (ORCID: https://orcid.org/0000-0002-2781-2346)
- Jihang Gao (ORCID: https://orcid.org/0009-0000-7306-5428)
- Yandong He (ORCID: https://orcid.org/0000-0002-3281-4493)
- Linxiao Shen (ORCID: https://orcid.org/0000-0001-7933-3673)
- Jie Li (ORCID: https://orcid.org/0009-0005-5218-7625)
- Ru Huang
- Yaohui Luan
Institutions
- Peking University (CN)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719507
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China