A Switched-Capacitor SRAM In-memory Computing Macro with High-precision, High-efficiency Differential Architecture

This paper presents an $1152 \times 256$ switched-capacitor (SC) SRAM in-memory computing (IMC) macro in 28 nm CMOS. SC IMC has enabled high-SNR analog computation, wherein ADC quantization now poses the critical precision and energy limitation. This limitation is addressed in this work by: (1) a fully differential architecture, which enables doubling of the supply-limited signal swing, allowing the ADC dynamic range to be efficiently increased to 10 b; (2) ADC sharing across either two or four binary-weighted columns to amortize energy and area; (3) configurable non-uniform quantization, optimized for the high concentration of data from IMC computation typically around the ADC mid-range. The macro achieves state-of-art (SoA) energy efficiency of 8161 TOPS/W and compute-density of 111.8 TOPS $/ \mathrm{mm}^{2}$, both normalized to 1-b computations. In addition to high IMC compute precision, neural-net (NN) classification is demonstrated by mapping ResNet-18 to the prototype, performing both CIFAR-10 and the more complex ImageNet tasks, both achieving ideal-level accuracies of $\mathbf{9 2. 3 4 \%}$ and 69.88%, respectively.