A Type-II Reference-Sampling PLL with Non-Uniform Octuple-Sampling Phase Detector Achieving 55-fs Jitter<sub>RMS</sub>, –91.9-dBc Reference Spur and –259-dB Jitter-Power FOM
A type-II reference-sampling phase-locked loop (PLL) with a non-uniform octuple-sampling phase detector (PD) is proposed to lower the PD’s in-band phase noise without raising the PLL’s input load and crystal oscillator’s power consumption. A low-noise multi-modulus divider and clock generator are utilized to generate sampling clocks without power-hungry retimers, further improving the jitter-power Figure-of-Merit (FOM). With a $150-\mathrm{MHz}$ input reference, the prototype in 28-nm CMOS achieves an RMS jitter of 55 fs and a $F O M$ of $\mathbf{- 2 5 9} \mathrm{dB}$ with a spur level of -91.9 dBc. The total power consumption is 3.34 mW at 4.8 GHz.
Authors
- Yunbo Huang (ORCID: https://orcid.org/0000-0002-1355-7583)
- Tetsuya Iizuka (ORCID: https://orcid.org/0000-0002-1512-4714)
- Bo Li (ORCID: https://orcid.org/0000-0003-4905-2744)
- Pui‐In Mak (ORCID: https://orcid.org/0000-0002-3579-8740)
- H. Ren (ORCID: https://orcid.org/0009-0008-8564-9904)
- Zunsong Yang (ORCID: https://orcid.org/0000-0001-8539-8481)
- Tianle Chen (ORCID: https://orcid.org/0009-0000-5930-0145)
- Weidong Zhang (ORCID: https://orcid.org/0000-0002-4700-1276)
- Yong Chen (ORCID: https://orcid.org/0000-0002-2794-1324)
- Xianghe Meng (ORCID: https://orcid.org/0000-0003-1185-2201)
- Zhongmao Li (ORCID: https://orcid.org/0000-0002-1108-4284)
- Weiwei Yan (ORCID: https://orcid.org/0009-0005-2953-8802)
Institutions
- Chinese Academy of Sciences (CN)
- University of Macau (MO)
- Institute of Microelectronics (CN)
- The University of Tokyo (JP)
- Tsinghua University (CN)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719490
- Citations
- 2
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.42