A 28 nm RRAM-Based 81.1 TOPS/mm²/bit Compute-In-Memory Macro with Uniform and Linear 64 Read Channels under 512 4-bit Inputs

The rapid development of AI models imposes stringent demands on computing density at edge side. High parallelism computing-in-memory (CIM) macro with multi-level weights and analog inputs can meet the requirements. This work proposes a dual-loop clamping ADC to attain linear and uniform readouts, along with an incremental integration scheme to suppress thermal noise. A novel segmented array structure is employed to enhance computing flexibility with configurable parallelism. Based on these innovations, a 28 nm high-parallelism resistive random-access memory (RRAM) CIM macro with 4-bit weight and 4 -bit inputs is reported to attain a state-of-the-art normalized computing density of $81.1 \mathrm{TOPS} / \mathrm{mm}^{2} /$ bit with the largest 512 parallelism. In addition, this work reports high linearity (0.9985 of $\mu\left(\mathrm{R}^{2}\right)$ and uniformity $\left(0.0003\right.$ of $\sigma\left(\mathrm{R}^{2}\right)$ across 64 parallel ADCs for the first time.