A 2.5mW Fully-Passive 2<sup>nd</sup>-Order Noise-Shaping Bang-Bang PLL with Adaptive DCO Gain Controller Achieving 305-fs<sub>rms</sub> Jitter and –246.3 dB FoM

A fully-passive second-order noise-shaping bangbang phase-locked loop with adaptive DCO gain controller is introduced. The proposed noise shaping technique effectively reduces the quantization noise generated by the bang-bang phase detector, which is a major influence on the integrated root-mean-square(rms) jitter. The proposed noise-shaping PD adopts a compact timing and fast-response circuit structure, which reduces the loop latency and ensures the loop stability with limited power consumption. In addition, the proposed automatic gain calibration, operating in background manner, optimizes the loop bandwidth and reduces the in-band phase noise by 6 dB. The proposed phase-locked loop is fabricated in 65 nm process with a core area of 0.12 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The power consumption of the core circuit is 2.50 mW at an output frequency of 4.8 GHz, and it achieves 305 fs rms jitter. The figure of merit (FoM) reaches –246.3 dB.

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Published
2024-09-09
DOI
https://doi.org/10.1109/esserc62670.2024.10719475
Citations
1
Primary Topic
Advancements in PLL and VCO Technologies
Type
article
Field-Weighted Citation Impact
0.21

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article

A 2.5mW Fully-Passive 2nd-Order Noise-Shaping Bang-Bang PLL with Adaptive DCO Gain Controller Achieving 305-fsrms Jitter and –246.3 dB FoM

Xin Yu, Zhijie Chen, Zijing Yuan, Peiyuan Wan et al.
1 citations
Advancements in PLL and VCO Technologies
0.21
article

A 2.5mW Fully-Passive 2nd-Order Noise-Shaping Bang-Bang PLL with Adaptive DCO Gain Controller Achieving 305-fsrms Jitter and –246.3 dB FoM

Xin Yu, Zhijie Chen, Zijing Yuan, Peiyuan Wan, Qianshui Yu, Xu Liu, Wei Deng
article en
1 citations

Abstract

A fully-passive second-order noise-shaping bangbang phase-locked loop with adaptive DCO gain controller is introduced. The proposed noise shaping technique effectively reduces the quantization noise generated by the bang-bang phase detector, which is a major influence on the integrated root-mean-square(rms) jitter. The proposed noise-shaping PD adopts a compact timing and fast-response circuit structure, which reduces the loop latency and ensures the loop stability with limited power consumption. In addition, the proposed automatic gain calibration, operating in background manner, optimizes the loop bandwidth and reduces the in-band phase noise by 6 dB. The proposed phase-locked loop is fabricated in 65 nm process with a core area of 0.12 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The power consumption of the core circuit is 2.50 mW at an output frequency of 4.8 GHz, and it achieves 305 fs rms jitter. The figure of merit (FoM) reaches –246.3 dB.

Beijing University of Technology (CN), Tsinghua University (CN)
National Natural Science Foundation of China
Affordable and clean energy
Openalex Percentile: Top 47%
Advancements in PLL and VCO Technologies
0.21
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