A 0.07-pJ/bdB 32-Gb/s Receiver with Pattern-Based Baud-Rate CDR and DFE Adaptation Using 2UI Integrator without Data-Level Reference

This paper presents a 32-Gb/s receiver with a pattern-based baud-rate clock and data recovery (CDR) and a decision feedback equalizer (DFE) adaptation using a 2UI integrator. The 2UI integrator integrates two unit intervals (UIs) from the edge of data. By utilizing the integrated outputs with the sampled data, the baud-rate CDR and the 1-tap DFE adaptation are performed without a data-level reference (dLev). Therefore, the proposed receiver only uses zero-crossing samplers, saving the power consumption and chip area. Moreover, the proposed baud-rate CDR using the 2UI integrator is less sensitive to the channel condition compared to the conventional baud-rate CDRs. Fabricated in a 40-nm CMOS technology, the prototype receiver achieves a bit error rate (BER) less than $10^{-12}$ at $32 \mathrm{~Gb}/\mathrm{s}$ over a 16-dB loss channel. The receiver occupies an active area of 0.026 $\mathrm{mm}^{2}$ and consumes 38.04 mW, achieving an energy efficiency of $1.19 \mathrm{pJ} / \mathrm{b}$.