A Novel DTCO-driven 1T1R Bitcell for sub-10ns STT-MRAM LLC Macros at N12 Node

We introduce a novel 1T1R bitcell design to address the challenges posed by the high current requirement during the Parallel to Anti-Parallel (P2AP) transition in STT-MRAM. This innovative configuration enhances the entire subarray’s resistive write-path when supported by thorough design technology co-optimization (DTCO). Delivering >80% current for P2AP switching, the proposal enables larger subarray capacities while allowing for a simplified periphery and biasing framework. Our proposal overcomes a major barrier that previously hindered the write speed and delayed the adoption of STT-MRAM technology for embedded Last Level Caches (LLCs). The designed $256 x 256$ subarrays simulated in commercial N12/N22 nodes prove technology node scaling and showcase exceptional write performance, $6.6 / 9.55 {ns}$ respectively, enabling a wide range of macros (8KB-1MB) operating below 10ns.