Understanding the Electrical Impact of DTI Induced Dislocations on Smart Power Devices

This work presents a detailed analysis of the electrical effect of silicon dislocations generated from the Deep Trench Isolation (DTI) module on a HV power MOSFET integrated in a proprietary $0.13 \mu \mathrm{~m}$ BCD platform. The impact of such defects on yield is strongly dependent on device architecture and doping, therefore resulting in extremely different failure rates for n-channel and p-channel devices. The explanation lies in the interaction between the dislocation and the $n+$ buried layer, resulting in an alteration of the Reduced Surface Field (ReSurF) effect on the device, and thus reducing its voltage capability. This is proven both by TCAD and by dedicated drain implant engineering trials. Moreover, the electrical measurement of a dislocation-based FET, embedded within the power device, is shown, and discussed.