A 0.25–2.7 GHz, 0.6 V, 1.59 mW Auxiliary-Path-Free Noise-Cancelling Low-Noise Amplifier in 28 nm CMOS

An inductorless wideband auxiliary-path-free noise-cancelling (NC) low-noise amplifier (LNA) with current reuse is proposed. In conventional NC technique, the noise of the main amplifier is cancelled by adding an auxiliary amplifier, which introduces additional noise and consumes extra power. In the proposed work, the noise of the main amplifier can be suppressed at zero theoretically while no additional auxiliary amplifier is required. Moreover, the complementary current reuse structure is exploited in this work for power reduction. Fabricated in 28 nm CMOS, the LNA exhibits a voltage gain of 17.7 dB with a 3-dB bandwidth of 0.25 to 2.7 GHz, a minimum noise figure (NF) of 2.9 dB at 1.2 GHz and an IIP3 of 6.8dBm at 1 GHz. It consumes 1.59 mW from a 0.6 V supply and occupies a very compact die area of $0.0076 \mathbf{~ m m}^{2}$.

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Published
2024-09-09
DOI
https://doi.org/10.1109/esserc62670.2024.10719426
Citations
1
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.18

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article

A 0.25–2.7 GHz, 0.6 V, 1.59 mW Auxiliary-Path-Free Noise-Cancelling Low-Noise Amplifier in 28 nm CMOS

Rucheng Jiang, Chirn Chye Boon, Zhe Liu
1 citations
Analog and Mixed-Signal Circuit Design
0.18
article

A 0.25–2.7 GHz, 0.6 V, 1.59 mW Auxiliary-Path-Free Noise-Cancelling Low-Noise Amplifier in 28 nm CMOS

Rucheng Jiang, Chirn Chye Boon, Zhe Liu
article en
1 citations

Abstract

An inductorless wideband auxiliary-path-free noise-cancelling (NC) low-noise amplifier (LNA) with current reuse is proposed. In conventional NC technique, the noise of the main amplifier is cancelled by adding an auxiliary amplifier, which introduces additional noise and consumes extra power. In the proposed work, the noise of the main amplifier can be suppressed at zero theoretically while no additional auxiliary amplifier is required. Moreover, the complementary current reuse structure is exploited in this work for power reduction. Fabricated in 28 nm CMOS, the LNA exhibits a voltage gain of 17.7 dB with a 3-dB bandwidth of 0.25 to 2.7 GHz, a minimum noise figure (NF) of 2.9 dB at 1.2 GHz and an IIP3 of 6.8dBm at 1 GHz. It consumes 1.59 mW from a 0.6 V supply and occupies a very compact die area of $0.0076 \mathbf{~ m m}^{2}$.

National University of Singapore (SG), Nanyang Technological University (SG)
Ministry of Education
Affordable and clean energy
Openalex Percentile: Top 51%
Analog and Mixed-Signal Circuit Design
0.18
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A 0.25–2.7 GHz, 0.6 V, 1.59 mW Auxiliary-Path-Free Noise-Cancelling Low-Noise Amplifier in 28 nm CMOS — Rucheng Jiang, Chirn Chye Boon, et al. · (2024) | TGRS Research Map | TGRS