A 153μW 26nV/√Hz Readout Circuit with BW and Power Scalability Using Capacitively-Coupled Chopper Floating Inverter Amplifier Embedded in a Discrete-Time ΔΣ Modulator

This paper presents an energy-efficient low-noise readout circuit that consists of a capacitively-coupled chopper floating inverter amplifier (CCFIA) embedded in a discrete-time (DT) Delta-Sigma modulator $(\Delta \Sigma M)$. The dynamic bandwidth of the CCFIA not only ensures fast settling but also prevents excessive noise folding in the succeeding switched-capacitor DT $\Delta \Sigma M$, thus achieving high energy efficiency. Moreover, the use of the CCFIA allows the power consumption of the readout circuit to be scalable with its sampling frequency ($f_{S}$) or signal bandwidth (BW), offering a flexible and efficient solution to low-power multi-sensing systems, where signals with different BW must be acquired in different scenarios. With a 2.56 MHz sampling frequency, the readout circuit achieves 84.9 dB dynamic range (DR), 83.9dB SNDR (62 mV input), and $26 \mathrm{nV} / \sqrt{ } \mathrm{Hz}$ input-referred noise density within a 10 kHz BW, while consuming $153 \mu \mathrm{~W}$. This leads to a 177.5 dB FoM and a 9.3 noise efficiency factor (NEF).