A 4-Channel 60Gb/s Aggregate & 0.167pJ/bit/dB Transceiver Achieving 33% Higher Pin-Efficiency Over Differential Using 4b6w Balanced Coding

This paper presents a transceiver using balanced coding with higher pin efficiency while without compromising the signal-to-noise ratio (SNR). The proposed transceiver architecture utilizes a 4b6w (4 bits over 6 wires) balanced encoding technique to achieve 0.66 pin efficiency, which is $33 \%$ higher than fully differential. The Rx front end is designed to differentially sense the six lanes to achieve 3dB higher SNR over single-ended. The proposed transceiver achieves a $60 \mathrm{~Gb} / \mathrm{s}$ aggregate data rate $(15 \mathrm{~Gb} / \mathrm{s} / \mathrm{ch})$ and compensates for 15 dB channel loss at 7.5 GHz with an FoM of $0.167 \mathrm{pJ} / \mathrm{bit} / \mathrm{dB}$ in 16 nm FinFET.