A Reliable 2 bit MLC FeFET with High Uniformity and 10⁹ Endurance by Gate Stack and Write Pulse Co-optimization

Multi-level cell (MLC) ferroelectric FETs (FeFETs) encounter the critical reliability challenges of poor device uniformity and limited endurance. In this work, a holistic strategy leveraging gate stack engineering and optimal write voltage pulses was proposed to co-optimize the uniformity and endurance of FeFETs. By inserting a thin Al<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> layer in the middle of the ferroelectric Zr-doped $\mathbf{H f O}_{2}$ (HZO) layer, the device-to-device variation is suppressed due to grain size reduction, and gate leakage is effectively blocked to prevent early breakdown. Writing scheme is also optimized by applying voltage pulses with larger magnitude and shorter width, which is found to benefit both the uniformity and endurance. The combined device structure and write scheme optimization reduces the average memory states variation by 36% for a reliable 2 bit MLC, and enables a state-of-the-art endurance of more than $10^{9}$ cycles.