A 1.22fJ/cycle 17T Pseudo-Static True Single-Phase Clock Flip-Flop in 14nm FinFET CMOS

This paper presents an energy-efficient 17T pseudostatic true single-phase clock flip-flop that eliminates redundant switching, contention, and output glitches with significantly improved retention time. Fabricated in a 14nm FinFET CMOS process, the design only consumes $1.22 \mathrm{fJ} /$ cycle and demonstrates up to 67.7% energy reduction and 26.4% smaller clock-to-q delay compared to TGFF. The worst-case minimum operating frequency is measured at 625 kHz, making it an attractive solution for both low-power and high-performance systems.