A 3.32mW 300MS/s 13b Pipelined SAR ADC Using a Time-Assisted Ringamp with Dynamic Slew Rate and Low-Supply Bias

This paper presents a time-assisted ringamp topology that relaxes the tradeoff between speed and accuracy in conventional ringamps. In this topology, a time-domain voltage-to-time converter (VTC) enables high speed by boosting the slew rate of the ringamp during coarse open-loop amplification and releases the slew rate for high gain and stability during close-loop fine settling. The Proposed ringamp adopts a dynamic feedback Class-AB bias that needs a supply of only $V_{\mathrm{gs}, \min }+2 V_{\text {dsat }}$ for larger supply headroom; it also eliminates the level-shifting capacitors as in prior works to achieve higher area efficiency and lower parasitic capacitance. A two-stage pipelined SAR ADC in 40 nm CMOS equipped with the proposed techniques achieves a measured SNDR of 67.1 dB and a SFDR of 79.3 dB at $300 \mathrm{MS} / \mathrm{s}$, while consuming 3.32 mW in a 1.1 V supply.