High Density 360 /μm Aligned CNT FET with I<sub>ON</sub> &gt;1 mA/μm at -0.5 V V<sub>D</sub> and 30nm L<sub>ch</sub>

In this work, we demonstrate high performance FETs integrated on high density aligned carbon nanotube (ACNT) arrays and perform statistical analysis. The back-gate pFETs show $I_{\text {on }}\gt 1.2 \mathrm{~mA} / \mu \mathrm{m}, R_{\mathrm{c}} \sim 91 \Omega \cdot \mu \mathrm{~m}$, whereas the dual-gate pFETs show $I_{\text {on }} \sim 800 \mu \mathrm{~A} / \mu \mathrm{m}$, on-off ratio $\sim 5 \times 10^{3}$ at 30 nm channel length $\left(\mathrm{L}_{\mathrm{ch}}\right)$ and $-0.5 \mathrm{~V} \mathrm{~V}_{\mathrm{d}}$. The impact of gate dielectric, EOT scaling and post-fabrication annealing on the device performance are explored in batch. With process optimization, the on-state performance of dual-gate A-CNT FETs is approaching silicon technology.

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Published
2024-09-09
DOI
https://doi.org/10.1109/esserc62670.2024.10719532
Primary Topic
Semiconductor materials and devices
Type
article
Field-Weighted Citation Impact
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article

High Density 360 /μm Aligned CNT FET with ION >1 mA/μm at -0.5 V VD and 30nm Lch

Jean‐François de Marneffe, Marina Y. Timmermans, Zaoyang Lin, Thomas Nuytten et al.
Semiconductor materials and devices
article

High Density 360 /μm Aligned CNT FET with ION >1 mA/μm at -0.5 V VD and 30nm Lch

Jean‐François de Marneffe, Marina Y. Timmermans, Zaoyang Lin, Thomas Nuytten, Steven Brems, Daire Cott, César Javier Lockhart de la Rosa, Gouri Sankar Kar, Fengben Xi, Himanshu Sharma, Luca Mana, Han Han, Lijun Liu, Xiangyu Wu, Ludovic Goux, Dennis Lin
article en

Abstract

In this work, we demonstrate high performance FETs integrated on high density aligned carbon nanotube (ACNT) arrays and perform statistical analysis. The back-gate pFETs show $I_{\text {on }}\gt 1.2 \mathrm{~mA} / \mu \mathrm{m}, R_{\mathrm{c}} \sim 91 \Omega \cdot \mu \mathrm{~m}$, whereas the dual-gate pFETs show $I_{\text {on }} \sim 800 \mu \mathrm{~A} / \mu \mathrm{m}$, on-off ratio $\sim 5 \times 10^{3}$ at 30 nm channel length $\left(\mathrm{L}_{\mathrm{ch}}\right)$ and $-0.5 \mathrm{~V} \mathrm{~V}_{\mathrm{d}}$. The impact of gate dielectric, EOT scaling and post-fabrication annealing on the device performance are explored in batch. With process optimization, the on-state performance of dual-gate A-CNT FETs is approaching silicon technology.

IMEC (BE)
Graphene Flagship
Openalex Percentile: Top 84%
Semiconductor materials and devices
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