Area-Efficient CFET Dual-port SRAM with Backside Interconnect
We propose a Complementary FET (CFET) compatible dual-port Static Random-Access Memory (SRAM) bit-cell design with backside interconnect. This design aims to match the footprint of an 8T dual-port bit-cell with that of a conventional 6T single-port bit-cell. The resulting CFET dualport SRAM achieves a dual-port to single-port footprint ratio of 1.175, nearing the theoretical minimum of 1 possible with CFET device architecture. This represents a significant improvement over the usual 1.51 footprint ratio in non-CFET nodes.
Authors
- Anita Farokhnejad
- M. García-Bardon
- Lynn Verschueren (ORCID: https://orcid.org/0000-0002-2941-769X)
- Dawit Burusie Abdi
- Fernando Garćıa-Redondo (ORCID: https://orcid.org/0000-0001-7090-8821)
- Geert Hellings (ORCID: https://orcid.org/0000-0002-5376-2119)
- Juergen Boemmels (ORCID: https://orcid.org/0000-0002-8761-5213)
- Pieter Weckx (ORCID: https://orcid.org/0000-0003-4579-0571)
- Moritz Brunion (ORCID: https://orcid.org/0000-0001-7842-7774)
- Julien Ryckaert (ORCID: https://orcid.org/0009-0001-0140-3042)
Institutions
- IMEC (BE)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719562
- Citations
- 3
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.63