A 28-nm 0.8M-weights/mm² 9.1-TOPS/mm² SRAM-Based All-Analog Compute-In-Memory Using Fine-Grained Structured Pruning with Adaptive-Ranging ADC

A 0.8M-weights $/ \mathrm{mm}^{2}$ 9.1-TOPS/mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> SRAMbased all-analog CIM for AI edge devices has been developed in 28-nm CMOS. This paper presents the first CIM for both efficient storing and processing of sparse weight matrices using fine-grained structured pruning, achieving 5.5x improvement in both memory and compute density. All-analog operations from MAC, biasing, ReLU to layer-to-layer quantization achieve high system-level energy efficiency and low latency. They are enabled by a PVT-tracking adaptive-ranging ADC with sensing margin improved by up to 576x. The proposed CIM achieves >6x higher memory and compute density than other CIMs with 116 TOPS/W system-level energy efficiency and low latency.