A 13b 280MS/s Partial-Interleaving Pipelined-SAR ADC with Active Bias-Enhanced Ring Amplifier and Background Calibration

In this paper, a compact 13b 280MS/s partial-interleaving (PI) pipelined-SAR ADC with inter-stage ring amplifier sharing is presented, which improves the conversion speed while maintaining low power consumption. To improve the settling speed, an active bias-enhanced ring amplifier is proposed. A background calibration is employed for gain error and timing skew in the first pipeline stage. The prototype ADC achieves 59.5 dB SNDR and 70.7 dB SFDR with Nyquist input frequency. Consuming 9.6 mW at 1.2 V supply, the Walden FoM and Schreier FoM are $44.4 \mathrm{fJ} /$ conv.-step and 161.1 dB, respectively.