Design Space Exploration of Oxide Semiconductorbased Monolithic 3D Gain Cell Memory

We present a comprehensive design space exploration of two transistor (2T) monolithic 3D (M3D) gain cell using amorphous oxide semiconductor (AOS). We particularly study the impact of two critical, yet unexplored parameters device variation and reliability on the performance of the gain cell memory. For this, we fabricate Tungsten-doped Indium Oxide (IWO) transistors with 100 nm gate length (Lg). We experimentally demonstrate (a) extremely low off-state leakage current (IOFF) of $0.1 \mathrm{fA} / \mu \mathrm{m}$, (b) high on-current (ION) $131 \mu \mathrm{~A} / \mu \mathrm{m}$ at $\lt 2 \mathrm{~V}$ overdrive (c) optimization of threshold voltage ($\mathrm{V}_{\mathrm{T}}$) using various process conditions, (d) device-to-device $V_{T}$ variation for $\mathbf{L g}=50 \mathrm{~nm}$ to $1 \mu \mathrm{~m}$, and (e) bias stress-induced $V_{T}$ shift of 150 mV, 30 mV and 200 mV for positive bias stress (PBS), negative bias stress (NBS) and hot carrier degradation (HCD) under 1000s bias stress. Using experimentally calibrated Virtual Source Model, we simulate 2T gain cell memory and investigate (a) cooptimization of VTS of write and read transistors for high-speed memory operation with long retention, (b) impact of device variation of memory operation including bit error rate, and (c) impact of bias stress induced $V_{T}$ shift on read/write speed, retention time and bit error rate. Overall, we highlight the key technological gaps between current research progress in AOS transistors with desired device targets for practical realization of gain cell memory with error-free fast read/write operation $(\lt 1 \mathrm{~ns})$ and long data retention time $(100 \mathrm{~ms})$.