A Compact 0.1-19.7GHz Ultra-Wideband Power Amplifier with ±0.5dB Gain Ripple in 28 nm CMOS Process

This paper presents a 0.1-19.7GHz ultra-wideband two-stage power amplifier(PA) in 28nm CMOS process. Driven by the pole-zero analysis of the proposed T-coil input matching network, the PA achieves a low return loss across the whole frequency band. Bandwidth expansion inductance of the inter-stage matching introduces a peak at high frequency to improve voltage gain, while the output matching network considers ESD capacitance and provides another complex poles to further compensate for the gain drop. Based on the peak frequency staggering tuning scheme, the proposed PA achieves a state-of-art bandwidth and low gain ripple. The PA demonstrated a 9.1-11.6dBm saturated power(Psat) and 4.5-5.6dBm OP1dB with power added efficiency (PAE) of 3.9-7.7%. The measured S11 remains below -11dB and the fractional bandwidth(FBW) is 1396.4%(0.1-19.7GHz) with ±0.5dB ripple in a compact area of 0.234mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.