Cache-PIM: An ECC-compatible eDRAM-PIM for Last-Level Cache with Resolution-aware Single-Cycle Voting

Cache-PIM, an eDRAM-PIM-based last-level cache, is proposed for implementing the PIM system into real-world memory architectures. An ECC-compatible eDRAM-PIM enables reliable in-memory computing even in less stable DRAM environments while reducing ECC latency for PIM tasks. Resolution-aware single-cycle voting reduces noise vulnerability induced by ADC truncation in analog multi-bit operation. The Cache-PIM is fabricated in 28 nm CMOS technology and occupies $0.66 \mathrm{~mm}^{2}$ die area. A demonstration of ResNet-18 on the ImageNet dataset achieves $\mathbf{4 3. 0 \%}$ latency reduction compared to the conventional ECC and 69.6% accuracy.