Experimental Evaluation of 7-Level Stacked Nanosheet SOI MOSFETs Analog Parameters
This study assesses the analog parameters of 7-level stacked SOI nanosheet transistors. The impact of nanosheet width, channel length, and bias condition is thoroughly examined through the analysis of experimental data. Key parameters, including transconductance, output conductance, and intrinsic voltage gain, are used as figures of merit for this investigation. A comparative analysis with data available in the literature reveals that the intrinsic voltage gain exhibits less sensitivity to nanosheet width when compared to single-level and 2-level stacked nanosheets.
Authors
- F. E. Bergamaschi (ORCID: https://orcid.org/0000-0002-0927-7407)
- Jaime Calçade Rodrigues (ORCID: https://orcid.org/0000-0002-3731-2206)
- Michelly de Souza (ORCID: https://orcid.org/0000-0001-6472-4807)
- M. Cassé (ORCID: https://orcid.org/0000-0002-4934-2445)
- Sylvain Barraud (ORCID: https://orcid.org/0000-0002-4334-9638)
- Lucas Mota Barbosa da Silva (ORCID: https://orcid.org/0000-0003-1257-9729)
- Marcelo Antonio Pavanello (ORCID: https://orcid.org/0000-0003-1361-3650)
- O. Faynot
Institutions
- Centro Universitário FEI (BR)
- Commissariat à l'Énergie Atomique et aux Énergies Alternatives (FR)
- Laboratoire d'Électronique des Technologies de l'Information (FR)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719505
- Citations
- 3
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.63