A 18 nm FD-SOI CMOS 6.38 mW 15 fps 8 -bit features 14.8 μJ/inference QVGA road-traffic monitoring Edge AI SoC demonstrator
This paper presents an autonomous road traffic monitoring Edge AI SoC implemented in 18nm FD-SOI CMOS. The SoC includes a RISC-V CPU, a 128 Processing Elements (PE) Single Instruction Multiple Data (SIMD) Tensor Processing Unit (TPU) AI accelerator, with QVGA and control interfaces. It uses Adaptative-Body-Bias (ABB) process and temperature compensation. The circuit operates within 0.5 to $0.87 \mathrm{~V},-40$ to $140^{\circ} \mathrm{C}, 50$ to 500 MHz ranges. The TPU efficiency energy per inference and latency are $3.52 \mu \mathrm{~J}$ and 0.616 ms when running MobileNet v1 stripped by 2 layers, and $14.8 \mu \mathrm{~J}$ and 2.27 ms when running traffic monitoring application. For this latter application, the circuit total power is 6.38 mW at 15 fps 0.5 V supply.
Authors
- Sylvain Clerc
- Shelby Lacouture (ORCID: https://orcid.org/0000-0002-9449-8844)
- Roberto Guizzetti
- Damien Riquet (ORCID: https://orcid.org/0009-0004-9835-9878)
- Stefano Bernabovi
- A. Benalla
- Christophe Blanc (ORCID: https://orcid.org/0000-0002-8470-478X)
- Bruno Paille
- Christophe Lecocq
- Didier Gueze
- Stephane Hulot
- A. Lafage
- Sébastien Marchal
- Vincent Heinrich
- R. Gras
- F. Arnaud (ORCID: https://orcid.org/0000-0002-8426-6695)
- Andreia Cathelin (ORCID: https://orcid.org/0000-0003-2745-4523)
- Fabien Nimsgern
- Nathan Bain
- Emilien Taly
- Ali Oudrhiri
- Mohamed Djouder (ORCID: https://orcid.org/0009-0004-9698-4741)
- O. Weber
- Robin Wilson
- David Bousquet
- Pascal Urard
- Jerome Potot
- Christophe-Victor Mangano
- Sylvain Biard
- Lucille Krauth
- Alexandre Blampey
Institutions
- Délégation Paris 7 (FR)
- STMicroelectronics (France) (FR)
- LIP6 (FR)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719433
- Primary Topic
- CCD and CMOS Imaging Sensors
- Type
- article
- Field-Weighted Citation Impact
- 0.00