Junction design for high performance backside-illuminated single photo avalanche diodes

We fabricated a SPAD (Single Photon Avalanche Diode) array using 40 nm CMOS technology with 3D stacked backside-illuminated (BI) process. The optimization of the junction profile was conducted for two distinct SPAD pixel designs, incorporating $\mathrm{N}+/ \mathbf{P}$ well junctions to minimize dark noise while maximizing photon detection efficiency. Additionally, the influence of the guard ring on device performance was assessed. With the junction design with guard ring, we found it difficult to increase PDE (Photon Detection Efficiency) due to the strong trade-off between PDE and DCR (Dark Count Rate) while with the conventional junction design without guard, we could achieve the significantly a notable high PDE of $37 \%$ at 940 nm wavelength through the junction profile optimization work. In this work, we conclude that the simple junction design without guard structure is desirable for small pixel pitch SPAD devices in terms of achieving highly competitive SPAD device performance.