A 14nm SRAM Using NMOS Header Assist Cell for Improved Write Ability and Reduced Cell Retention Leakage
This paper presents NMOS header assist cell (NHAC) that lowers SRAM VMin with minimal power overhead for low power applications. The proposed NHAC, featuring a bitcell-compatible layout, is inserted between cell arrays to provide cell power. NHAC achieves a VMIN improvement of 210 mV with 4% power overhead, even in the high interconnect resistance case, thanks to the continuous self-collapse of cell power voltage. Additionally, enabling all NHACs in sleep mode reduces bitcell retention leakage by 25% to 61% without additional area cost.
Authors
- Giseok Kim (ORCID: https://orcid.org/0000-0002-4699-1239)
- Keonhee Cho (ORCID: https://orcid.org/0000-0001-8014-0684)
- Seong‐Ook Jung (ORCID: https://orcid.org/0000-0003-0757-2581)
- Dong-Wook Seo (ORCID: https://orcid.org/0000-0001-9449-7772)
- Sangyeop Baeck (ORCID: https://orcid.org/0000-0002-9106-5461)
- Sekeon Kim (ORCID: https://orcid.org/0000-0001-5927-9390)
- Hyunjun Kim (ORCID: https://orcid.org/0000-0003-2101-8026)
- Jungmyung Kang
- Seiseung Yoon
Institutions
- Yonsei University (KR)
- Samsung (South Korea) (KR)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719479
- Citations
- 1
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.49
Funders
- Samsung