Cold CMOS for Sustainable Datacenters
Net benefits of cold CMOS including the refrigeration penalty are investigated for datacenters. It is found that cold CMOS is best used in the iso-speed (energy efficiency) scenario at moderately low temperatures above $-50^{\circ} \mathrm{C}$. Total energy reduction at iso-speed is $\mathbf{- 3 0 \%}$ with $\mathrm{LCO}_{2}\left(-50{ }^{\circ} \mathrm{C}\right)$ and $-10 \%$ with $\mathrm{LN}_{2}\left(77 \mathrm{~K},-196^{\circ} \mathrm{C}\right)$ for $\mathbf{4 0 \%}$ of Carnot cooling efficiency. The optimal die temperature is around $-20^{\circ} \mathrm{C}$. Highspeed scenario (same compute power) is less interesting because total energy increases more rapidly than delay reduces (2 X for $-\mathbf{2 0 \%}$ at $\left.-50{ }^{\circ} \mathbf{C}\right)$ and heat transfer is limited for $\mathbf{L N}_{2}(\lt 30$ $\mathrm{W} / \mathrm{cm}^{2}$). Overall, LCO<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>CMOS at iso-speed ($\mathrm{V}_{\mathrm{DD}} \approx 0.6 \mathrm{~V}$) can improve datacenter sustainability in terms of energy efficiency, power density, and environmental impact. Power density in emerging 3D stacked CMOS architectures can be reduced even if total-energy savings shrink to $-0 \%. \mathrm{LCO}_{2}$ is a welcome replacement for the fluorinated coolants being phased-out due to their high global warming potential of $25.000 \mathrm{CO}_{2}$-equivalent, and LCO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> batteries can store the fluctuating green energy while preserving rare-earth metal deposits and promoting geopolitical independence. To obtain more than $-\mathbf{3 0 \%}$ theoretical total energy reduction with voltage-scaled classical CMOS, further advances are required in cooling efficiency ($\gt 40 \%$) and/or (transistor) compute-power reduction ($\mathrm{V}_{\mathrm{DD}}\lt 0.6 \mathrm{~V}$). Further $\mathrm{V}_{\mathrm{DD}}$-scaling at iso-speed is hampered by the requirement to beat Boltzmann’s thermal limit. This could open up a new field of research on super-steep-slope devices achieving sub-thermionic behavior at moderately low temperatures instead of at room temperature.
Authors
- Maarten L. Van de Put (ORCID: https://orcid.org/0000-0001-9179-6443)
- Alexander Grill (ORCID: https://orcid.org/0000-0003-1615-1033)
- Geert Hellings (ORCID: https://orcid.org/0000-0002-5376-2119)
- M. Garcia Bardon (ORCID: https://orcid.org/0000-0001-5772-5406)
- Arnout Beckers (ORCID: https://orcid.org/0000-0003-3663-0824)
- Arvind Sharma (ORCID: https://orcid.org/0000-0002-9250-9642)
Institutions
- IMEC (BE)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719415
- Citations
- 1
- Primary Topic
- Semiconductor materials and devices
- Type
- article
- Field-Weighted Citation Impact
- 0.21