A 48-58GHz Frac-N DPLL achieving 137fs integrated jitter and fast locking time below 1μs

This work presents a 48-58GHz DTC based FracN DPLL with sub-1μs locking time for a 2 GHz frequency hopping. A Digital Hop Control (DHC), based on a digital pre-distortion and a two-point modulation scheme, is exploited to compensate oscillator’s non-linearity which allows the main loop to correct a smaller phase error, thus boosting the locking transient. The prototype has been fabricated in 28-nm CMOS technlogy, it achieves 137 fs inetgrated jitter in the 10 kHz -to25 MHz frequency range with 30 mW power consumption and worst in band frac-N spur level of -50.5 dBc (at 50 GHz). This design, working with a reference frequency of 100 MHz, achieves the best integrated jitter, FOMJ (-242.5 dB) and FOMN (-269.7 dB), among 30-60 GHzx fractional-N DPLLs.