A Robust Near-Zero Power Wakeup Timer With a Hybrid Reconfigurable FLL Directly Powered by Uncertain Harvested Voltage Down to 0.3V

Energy-harvesting systems require circuits to operate under ultra-low voltage supplies. Though the batteries are removed, a power management circuit is necessary to ensure a consistent voltage supply. In contrast to the state-of-the-art works, this work proposes a wakeup timer that is directly powered by harvested energy, thus obviating the need for additional power management circuits. In addition, we propose a hybrid FLL with an extended range of operation using digital-intensive architecture. Fabricated in 65 nm CMOS process, the chip consumes a total power consumption of 696 nW under 0.3 V supply. In addition, a temperature coefficient of $29 \mathrm{ppm} /{ }^{\circ} \mathrm{C}$, and a line sensitivity of $0.95 \% / \mathrm{V}$ are measured over a temperature/supply range of $0-100^{\circ} \mathrm{C}$ and $0.3-0.6 \mathrm{~V}$, respectively.

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Publication Details

Published
2024-09-09
DOI
https://doi.org/10.1109/esserc62670.2024.10719527
Citations
2
Primary Topic
Analog and Mixed-Signal Circuit Design
Type
article
Field-Weighted Citation Impact
0.37
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article

A Robust Near-Zero Power Wakeup Timer With a Hybrid Reconfigurable FLL Directly Powered by Uncertain Harvested Voltage Down to 0.3V

Chung-Ching Lin, Huan Hu, Wuchang Ding, Yutong Zhu
2 citations
Analog and Mixed-Signal Circuit Design
0.37
article

A Robust Near-Zero Power Wakeup Timer With a Hybrid Reconfigurable FLL Directly Powered by Uncertain Harvested Voltage Down to 0.3V

Chung-Ching Lin, Huan Hu, Wuchang Ding, Yutong Zhu
article en
2 citations

Abstract

Energy-harvesting systems require circuits to operate under ultra-low voltage supplies. Though the batteries are removed, a power management circuit is necessary to ensure a consistent voltage supply. In contrast to the state-of-the-art works, this work proposes a wakeup timer that is directly powered by harvested energy, thus obviating the need for additional power management circuits. In addition, we propose a hybrid FLL with an extended range of operation using digital-intensive architecture. Fabricated in 65 nm CMOS process, the chip consumes a total power consumption of 696 nW under 0.3 V supply. In addition, a temperature coefficient of $29 \mathrm{ppm} /{ }^{\circ} \mathrm{C}$, and a line sensitivity of $0.95 \% / \mathrm{V}$ are measured over a temperature/supply range of $0-100^{\circ} \mathrm{C}$ and $0.3-0.6 \mathrm{~V}$, respectively.

Southern University of Science and Technology (CN), Film Independent (US)
Affordable and clean energy
Openalex Percentile: Top 43%
Analog and Mixed-Signal Circuit Design
0.37
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A Robust Near-Zero Power Wakeup Timer With a Hybrid Reconfigurable FLL Directly Powered by Uncertain Harvested Voltage Down to 0.3V — Chung-Ching Lin, Huan Hu, et al. · (2024) | TGRS Research Map | TGRS