Bi-Voltage Scaling via Cryo-CMOS Standard-Cell Library and Fully-Automated Design for 34% Power Reduction and 1.5× DVFS Efficiency Improvement at 4 K
The unique voltage scaling potential of transistors at cryogenic temperature is identified. To fully exploit such potential for maximized DVFS efficiency and power reduction of cryo-digital systems, the bi-voltage scaling scheme, along with the Cryo-CMOS standard-cell library, is proposed. By applying this design-agnostic and fully-automated flow to a RISC-V subsystem at $4 \mathrm{~K}, 34 \%$ power reduction and $1.5 \times$ DVFS efficiency improvement is achieved, compared to the conventional voltage scaling method.
Authors
- Feichi Zhou (ORCID: https://orcid.org/0000-0001-7756-1082)
- Longyang Lin (ORCID: https://orcid.org/0000-0002-4702-737X)
- Hao Yu (ORCID: https://orcid.org/0000-0002-2674-4118)
- Bocang Qiu (ORCID: https://orcid.org/0000-0002-2771-7939)
- Yida Li (ORCID: https://orcid.org/0000-0002-5675-582X)
- Ying‐Jie Zhu (ORCID: https://orcid.org/0000-0002-5044-5046)
- Haoran Lyu
- Zhengke Yang
- Xuye Wang (ORCID: https://orcid.org/0000-0002-0116-175X)
- Zhen Xing Kong (ORCID: https://orcid.org/0000-0003-1961-1306)
- Kai Chen (ORCID: https://orcid.org/0000-0001-8402-5800)
- Shenghua Zhou (ORCID: https://orcid.org/0000-0002-9271-6633)
- Jiamin Li (ORCID: https://orcid.org/0009-0009-0232-2138)
- Humiao Li
- Yiqing Lan
Institutions
- Southern University of Science and Technology (CN)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719550
- Citations
- 1
- Primary Topic
- Advancements in Semiconductor Devices and Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.21
Funders
- National Natural Science Foundation of China