Integration of High-k Metal Gate (HKMG) to Core/Peri Transistors of DRAM Addressing Reliability Issues

This paper describes a new integration method for high-k metal gate (HKMG) core/peri transistor for high-performance and low-power DRAM. The present integration method is focused to solve five reliability challenges; degradation of storage node contact recess dispersion, cell contamination by HKMG residue, gate-to-gate bridge, threshold voltage instability due to oxygen ingress, time-zero dielectric breakdown of HKMG. The success of this integration process highlights the potential of HKMG technology in meeting the increasing demands for DRAM.