A 54.6-65.1 GHz Multi-Path-Synchronized 16-Core Oscillator Achieving -131.4 dBc/Hz PN and 195.8 dBc/Hz FoMT at 10 MHz Offset in 65nm CMOS

This paper reports a 60 GHz oscillator that synchronizes 16 cores for phase noise (PN) reduction. The proposed multi-path synchronization technique introduces more synchronization paths for any oscillator cores in the array, which helps maintain a low PN penalty induced by the frequency mismatch among oscillator cores when the number of oscillator cores increases. Particularly, our 16-core oscillator is realized by synchronizing 4 identical groups, and each group is realized by a quad-core oscillator. The quad-core oscillator in each group also features a triple-path-synchronized topology that aids in suppressing the increased frequency mismatch between oscillator cores induced by the asymmetric transformer layout when the oscillation frequency goes up. Fabricated in a 65 nm CMOS process, the $54.6-\mathrm{to}-65.1 \mathrm{GHz}$ oscillator prototype measures a low PN of $-131.4 \mathrm{dBc} / \mathrm{Hz}$, resulting in a high FoM/FoMT of $190.9 / 195.8 \mathrm{dBc} / \mathrm{Hz}$ at a 10 MHz offset from 65.11 GHz, respectively.