A 22nm 9.51 TOPS/W Neural Engine with 2MB MRAM Leveraging Sparse-Orthogonal Walsh-Hadamard Transform Computations and Dynamic Power Gating
We present the first silicon implementation of a Walsh-Hadamard transform based neural network (WHT-NN) processor featuring 2MB MRAM for all-on-chip weight storage, targeting edge devices. The design overcomes the high leak-age and access time of MRAM with several schemes such as dynamic power gating and multi-clock domain double-buffered caching. Our processor demonstrates best-in-class 9.51 and 22.86 TOPS/W peak energy efficiencies for sparse convolution and fully-connected layers, respectively, in 22 nm CMOS.
Authors
- Dennis Sylvester (ORCID: https://orcid.org/0000-0003-2598-0458)
- Hyochan An (ORCID: https://orcid.org/0000-0002-6322-025X)
- Zichen Fan (ORCID: https://orcid.org/0000-0002-8181-2996)
- Hun-Seok Kim (ORCID: https://orcid.org/0000-0002-6658-5502)
- David Blaauw (ORCID: https://orcid.org/0000-0001-6744-7075)
- Qirui Zhang (ORCID: https://orcid.org/0000-0001-8113-3558)
- Pierre Abillama (ORCID: https://orcid.org/0000-0001-9523-6152)
- Yu Chen (ORCID: https://orcid.org/0000-0001-9890-9551)
- Kuan-Yu Chen (ORCID: https://orcid.org/0000-0002-4168-6446)
Institutions
- University of Michigan (US)
Publication Details
- Published
- 2024-09-09
- DOI
- https://doi.org/10.1109/esserc62670.2024.10719484
- Citations
- 2
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.42